The present invention relates, in general, to the field of integrated circuit ("IC") dynamic random access memory ("DRAM") devices. More particularly, the present invention relates to the operational control of DRAM devices utilizing a "boost-on-writes" technique which obviates the need to boost the word line on entry into precharge thereby reducing total precharge time and increasing overall device access time.
Conventional DRAM devices are designed utilizing a volatile, dynamic memory cell memory array architecture, with each cell generally comprising a single transistor and capacitor. Such cells are "volatile" in the sense that upon powerdown, the memory contents is lost and "dynamic" in the sense that they must be constantly refreshed to maintain the charge in the cell capacitor. The refresh operation is accomplished when the memory contents of a row of cells in the memory array is read by the sense amplifiers and the logic states in the cells that have been read are amplified and written back to the cells. DRAM devices are used primarily for memory reads and writes and are relatively inexpensive to produce in terms of die area. They do, however, provide relatively slow access times compared to other memory devices types and refresh, precharge and other DRAM related "overhead" operations must be completed as expeditiously as possible in order to provide acceptable data access times in modern which speed applications.
With respect to precharge operations in a typical DRAM device, the word lines are generally "boosted" above the power supply level (in the case of an N-channel transistor based memory array; or below in the case of a P-channel memory array) to improve the strength of the internal one (or zero) signal. In a representative DRAM design, a P-channel transistor based array is used and the word lines are driven low using an associated N-channel device which is formed in the grounded IC substrate. However, the use of a below circuit ground boost has the undesired effect of causing a forward bias condition to exist on the parasitic diodes of these N-channel devices, thereby limiting both the voltage and duration of the boost. As a consequence, in order to insure that all bits are written fully, prior art techniques have required that the word line be boosted upon each entry into a precharge operation, thereby delaying the duration of the precharge function by the time needed for the additional boost period and effectively decreasing overall device access time.